Taehyoun Oh | Digital Architecture | Best Researcher Award

Published on by Architecture Engineers

Prof. Dr. Taehyoun Oh | Digital Architecture | Best Researcher Award

Professor | Kwangwoon University | South Korea

Taehyoun Oh is an Associate Professor at Kwangwoon University specializing in high-speed I/O circuit design and advanced mixed-signal integrated systems. He brings extensive experience from both academia and industry, contributing to high-performance SerDes development, MIMO channel equalization, and signal-integrity innovation through impactful roles in major semiconductor organizations. His research focuses on high-speed chip-to-chip communication, MIMO crosstalk cancellation, low-power equalization architectures, and multichannel I/O design, leading to significant advancements in CMOS-based receiver architectures, adaptive calibration algorithms, and prototype implementations. He has authored influential journal papers, contributed to prominent conferences, and published a specialized book on high-speed I/O circuits, demonstrating consistent leadership in circuit innovation. His work has been recognized through best-paper distinctions, competitive research awards, and collaborative contributions across internationally respected research laboratories and design teams. His technical expertise, scholarly output, and continued commitment to advancing high-speed interface technologies position him as a leading contributor in the field. His research impact includes 115 citations, 26 publications, and an h-index of 5.

Profiles: Scopus | ORCID | Google Scholar

Featured Publications

1. Cho K.U., Gil J., Park C., Cho K.J., Shin J.W., Kim E.S., Eo Y.S., Harjani R., et al. A 3.5–4.7 GHz Fractional-N ADPLL with a low-power time-interleaved GRO-TDC of 6.2 ps resolution in 65 nm CMOS process. IEEE Access, 2024, 2.

2. Chung G., Cho K., Oh T. 2 Lanes × 2.65–6.4 Gb/s scalable IO transceiver with delay compensation technique in 65 nm CMOS process. J. Semicond. Technol. Sci., 2024, 24(3), 184–190.

3. Ahn J., Kim S., Kwon K., Park M., Gil J., Choi H., Kim N.Y., Kim E.S., Jung Y., et al. A 5.3–6.2 GHz Fractional-N frequency synthesizer with variable-gain automatic frequency calibration using cycle slips in 65 nm CMOS. Electronics, 2024, 14(22), 4368.

4. Oh T., Harjani R. A 12 Gb/s multichannel I/O using MIMO crosstalk cancellation and signal reutilization in 65 nm CMOS. IEEE J. Solid-State Circuits, 2013, 48(6), 1383–1397.

5. Oh T., Harjani R. A 6 Gb/s MIMO crosstalk cancellation scheme for high-speed I/Os. IEEE J. Solid-State Circuits, 2011, 46(8), 1843–1856.

Taehyoun Oh’s work advances the future of high-speed electronic systems by enabling faster, more reliable, and energy-efficient chip-to-chip communication essential for next-generation computing and data-driven technologies. His innovations in MIMO equalization, crosstalk cancellation, and high-speed I/O architecture contribute directly to enhancing semiconductor performance and strengthening the global electronics industry. His vision is to pioneer intelligent, scalable interface solutions that shape the backbone of future digital infrastructure.

Ramazan Yasar | AI and Automation in Architecture | Pioneer Researcher Award

Published on by Architecture Engineers

Assoc. Prof. Dr. Ramazan Yasar | AI and Automation in Architecture | Pioneer Researcher Award

Lecturer | Ankara University | Turkey

Assoc. Prof. Dr. Ramazan Yasar is a faculty member in the Department of Artificial Intelligence and Data Engineering at Ankara University, specializing in artificial intelligence, cryptography, algorithms, graph theory, big data technologies, machine learning, neutrosophic and fuzzy logic systems, data science, and natural language processing. He has served in progressive academic roles, including long-term instructional and research positions, and has contributed to institutional development through editorial leadership as Managing Editor of the Hacettepe Journal of Mathematics and Statistics. His work spans advanced mathematical structures, module theory, algebraic systems, and computational intelligence, reflected in numerous peer-reviewed publications in respected international journals. He has collaborated on projects exploring generalized extending conditions, exact submodules, annihilator conditions, rough groups, and intuitionistic fuzzy group-based algebraic models, demonstrating sustained contributions to theoretical mathematics and emerging intelligent technologies. His academic journey includes recognitions, editorial responsibilities, professional memberships, and active participation in international research platforms, supporting his commitment to advancing interdisciplinary scholarship. His research impact includes 23 citations, 11 publications, and an h-index of 3.

Profiles: Scopus | ORCID | Google Scholar

Featured Publications

1. Yasar R., Tercan A., When some complement of an exact submodule is a direct summand. Commun. Algebra, 2021, 49(10), 4304–4312.

2. Yasar R., C11-modules via left exact preradicals. Turk. J. Math., 2021, 45(4), 1757–1766.

3. Tercan A., Yasar R., Yücel C.C., Goldie extending property on the class of exact submodules. Commun. Algebra, 2022, 50(4), 1363–1371.

4. Tercan A., Yasar R., Weak FI-extending modules with ACC or DCC on essential submodules. Kyungpook Math. J., 2021, 61(2), 239–248.

5. Birkenmeier G.F., Kilic N., Mutlu F.T., Tastan E., Tercan A., Yasar R., Connections between Baer annihilator conditions and extending conditions for nearrings and rings. J. Algebra Appl., 2024, 2650050.

Ramazan Yasar’s research advances the theoretical foundations of algebra and intelligent systems, strengthening the bridge between mathematical structures and modern computational technologies. His contributions support the development of more reliable, explainable, and secure AI frameworks, offering long-term value to scientific innovation and emerging digital industries. Through sustained scholarly impact, he contributes to a global ecosystem that depends on rigorous mathematical reasoning for next-generation technological progress.