Peilin Shao | AI and Automation in Architecture | Young Researcher Award

Published on by Architecture Engineers

Assist. Prof. Dr. Peilin Shao | AI and Automation in Architecture | Young Researcher Award

Lecturer | Shanxi Datong University | China

Assist. Prof. Dr. Peilin Shao is a Lecturer at Shanxi Datong University specializing in intelligent manufacturing, with academic training in industrial and manufacturing systems engineering as well as mechanical design, manufacturing, and automation. He has been actively involved in advanced research on assembly process modeling, knowledge graph construction, and AI-driven inference, contributing to projects that integrate large language models with manufacturing knowledge systems and supporting intelligent decision-making in complex engineering processes. His work encompasses assembly deviation analysis, process knowledge graph frameworks, and intelligent question-answering methods, with publications in reputable journals such as the Proceedings of the Institution of Mechanical Engineers, Applied Sciences, and the International Journal of Advanced Manufacturing Technology, alongside conference contributions in intelligent networked systems. Dr. Shao has demonstrated research leadership through collaborative projects and scholarly contributions that advance intelligent manufacturing. His research impact includes 8 citations, 5 publications, and an h-index of 1.

Profiles: Scopus | ORCID

Featured Publications

1. Qiao L., Shao P., Zhao H., Huang Z., An assembly deviation calculation method based on surface deviation modeling for circumferential grinding plane. Proc. Inst. Mech. Eng. Part B: J. Eng. Manuf., 2021.

2. Shao P., Huang Z., Qiao L., A novel assembly knowledge graph construction framework enhanced by large language model. Int. J. Adv. Manuf. Technol., 2025, Accepted.

Dr. Peilin Shao’s work advances intelligent manufacturing by integrating large language models with assembly process knowledge, enabling smarter, data-driven engineering decisions. His vision is to accelerate industry transformation through AI-enabled knowledge engineering that fosters sustainable, high-precision, and globally competitive manufacturing practices.

Taehyoun Oh | Digital Architecture | Best Researcher Award

Published on by Architecture Engineers

Prof. Dr. Taehyoun Oh | Digital Architecture | Best Researcher Award

Professor | Kwangwoon University | South Korea

Taehyoun Oh is an Associate Professor at Kwangwoon University specializing in high-speed I/O circuit design and advanced mixed-signal integrated systems. He brings extensive experience from both academia and industry, contributing to high-performance SerDes development, MIMO channel equalization, and signal-integrity innovation through impactful roles in major semiconductor organizations. His research focuses on high-speed chip-to-chip communication, MIMO crosstalk cancellation, low-power equalization architectures, and multichannel I/O design, leading to significant advancements in CMOS-based receiver architectures, adaptive calibration algorithms, and prototype implementations. He has authored influential journal papers, contributed to prominent conferences, and published a specialized book on high-speed I/O circuits, demonstrating consistent leadership in circuit innovation. His work has been recognized through best-paper distinctions, competitive research awards, and collaborative contributions across internationally respected research laboratories and design teams. His technical expertise, scholarly output, and continued commitment to advancing high-speed interface technologies position him as a leading contributor in the field. His research impact includes 115 citations, 26 publications, and an h-index of 5.

Profiles: Scopus | ORCID | Google Scholar

Featured Publications

1. Cho K.U., Gil J., Park C., Cho K.J., Shin J.W., Kim E.S., Eo Y.S., Harjani R., et al. A 3.5–4.7 GHz Fractional-N ADPLL with a low-power time-interleaved GRO-TDC of 6.2 ps resolution in 65 nm CMOS process. IEEE Access, 2024, 2.

2. Chung G., Cho K., Oh T. 2 Lanes × 2.65–6.4 Gb/s scalable IO transceiver with delay compensation technique in 65 nm CMOS process. J. Semicond. Technol. Sci., 2024, 24(3), 184–190.

3. Ahn J., Kim S., Kwon K., Park M., Gil J., Choi H., Kim N.Y., Kim E.S., Jung Y., et al. A 5.3–6.2 GHz Fractional-N frequency synthesizer with variable-gain automatic frequency calibration using cycle slips in 65 nm CMOS. Electronics, 2024, 14(22), 4368.

4. Oh T., Harjani R. A 12 Gb/s multichannel I/O using MIMO crosstalk cancellation and signal reutilization in 65 nm CMOS. IEEE J. Solid-State Circuits, 2013, 48(6), 1383–1397.

5. Oh T., Harjani R. A 6 Gb/s MIMO crosstalk cancellation scheme for high-speed I/Os. IEEE J. Solid-State Circuits, 2011, 46(8), 1843–1856.

Taehyoun Oh’s work advances the future of high-speed electronic systems by enabling faster, more reliable, and energy-efficient chip-to-chip communication essential for next-generation computing and data-driven technologies. His innovations in MIMO equalization, crosstalk cancellation, and high-speed I/O architecture contribute directly to enhancing semiconductor performance and strengthening the global electronics industry. His vision is to pioneer intelligent, scalable interface solutions that shape the backbone of future digital infrastructure.